Semiconductor substrate and process for its production

ABSTRACT

The present invention provides a semiconductor substrate comprising a semiconductor layer  3  formed on a supporting substrate  1  with interposition of an insulating layer  3  therebetween, wherein a mark is formed in a region other than a surface region of the semiconductor layer; and a process for producing the semiconductor substrate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor substrate foruse in production of a semiconductor integrated circuit device such assemiconductor memories, microprocessors, and system LSIs; and a processfor production thereof. In particular, the present invention relates toa semiconductor substrate having thereon a mark for identification ofthe semiconductor substrates and the like, and a process for productionthereof.

[0003] 2. Related Background Art

[0004] The semiconductor substrate includes mirror-wafers which are adisk-shaped substrate produced by slicing an ingot and have at least oneface polished, and epitaxial wafers constituted of a mirror-wafer and asemicrystalline semiconductor layer formed on the mirror-wafer.

[0005] On the other hand, an SOI technique is widely known which forms asingle-crystalline semiconductor layer on an insulator or on a substratehaving an insulating layer. This product is called asilicon-on-insulator, or a semiconductor-on-insulator. The semiconductorsubstrate formed thereby is called an SOI substrate or an SOI wafer.

[0006] Three processes below are typical for producing SOI substrates:

[0007] (1) A SIMOX process (separation by ion-implanted oxygen) whichforms an SiO₂ layer by oxygen ion implantation into an Sisingle-crystalline substrate.

[0008] (2) A smart cut process which comprises the steps of implantinghydrogen ions into an Si single-crystalline substrate, bonding anothersubstrate, heat-treating it to grow microbubbles formed in theion-implanted layer, and separating the Si single-crystalline substrate.The SOI substrate produced by this process is known as Unibond. Thedetail thereof is disclosed in Japanese Patent Application Laid-Open No.5-211128 and its corresponding U.S. Pat. No. 5,374,564.

[0009] A modification of this process is known which comprises the stepsof implanting hydrogen ions by hydrogen plasma into an Sisingle-crystalline substrate, bonding another substrate thereon, andapplying high-pressure nitrogen gas to the side wall of the bondedsubstrates to separate the Si single-crystalline substrate at theion-implanted layer.

[0010] (3) A still another process for SOI substrate production is aprocess for transferring a porous semiconductor layer formed on a porousbody onto another substrate. This process is known to give a highestquality of the SOI substrate since the semiconductor layer can be formedby epitaxial growth on a porous body. Specific example are disclosed inJapanese Patent No. 2,608,351 and its corresponding U.S. Pat. No.5,371,037, Japanese Patent Application Laid-Open No. 7-302889 and itscorresponding U.S. Pat. No. 5,856,229, and Japanese Patent No. 2,877,800and its corresponding EP 0,867,917. The process shown in these patentand applications is advantageous in that the thickness of the SOI layeris uniform, crystal defect density can readily be decreased, the surfaceof the SOI layer has a good flatness, the equipment for the productionis inexpensive, a wide range of the SOI film thickness from severalhundred Å to about 10 μm can be produced with one equipment, and soforth.

[0011] When wafers pass through the production step of semiconductorintegrated circuit devices (device step), it is preferable that thewafers are identified individually. The identification of the wafers ishighly effective in managing the step history of the individual wafers,and is utilized in failure analysis, optimization of the step,production control, and so forth. The identification of mirror waferscan be conducted using a mark formed on the wafer surface with a laserbeam.

[0012]FIG. 18 shows a cross section of a wafer after thus laser marking.The region of the surface of the wafer irradiated with laser beam ismelted to become a recessed portion, and the wafer material repelled outfrom the recessed portion by melting solidifies on the periphery of therecessed portion in a shape of a somma as shown in FIG. 18. For example,in the case where the laser having a power of 220 mW is applied in dotonto the surface of a silicon wafer, the maximum diameter X1 of thedeformed region ranges from 0.04 mm to 0.05 mm, the diameter X2 of therecessed portion at the center ranges from 0.02 mm to 0.03 mm, the depthY1 of the recessed portion ranges from 2 μm to 3 μm, and the height Y2of the protruded portion ranges from 0.5 μm to 1.0 μm. These dimensionsvary depending on the laser power. In practice, laser beam is applied inpulse to form many dots partially overlapped or separately, therebypicturing a mark. The wafer material to be the somma may be disappear.It is possible that the mark without the somma is formed by adjustinglaser power, laser frequency or shot counts of laser. Shallow mark withsomma may be formed by low power laser. High power laser forms deep markwithout somma by scattering or spreading the material to be the somma.The mark on the mirror wafer is usually constituted from about 10alphanumerical characters, and denotes a specific ID number of each ofthe wafers. This is a normal method which is prescribed by theInternational Standard of SEMI.

[0013] Such a laser marking method is assumed for usual Si mirrorwafers, and the marking position is also prescribed in the SEMIStandard.

[0014]FIG. 19 is a top view of a mirror wafer 21 having a mark formedthereon, and FIG. 20 is a sectional view of the mirror wafer 21 at andaround the mark. For example, in a 8-inch wafer as shown in FIG. 19 witha notch 12 placed upward, taking the center 100 of the wafer as theorigin (0,0) of an x-y coordinate, the aforementioned SEMI Standardprescribes that a mark 4 should be formed in a marking region 24 where Xranges from −9.25 to +9.25 mm, Y ranges from +93.7 to +96.5 mm, that is,in a rectangular region 24 in the height L2 being 2.8 mm, the length L1being 18.5 mm.

[0015] If this standard is applied to the SOI wafer, the marking rangecomes to the surface region of the semiconductor layer (SOI layer) onthe insulating layer.

[0016]FIG. 21 is a top view of an SOI wafer having the mark formedthereon. FIG. 22 is a sectional view at and around the mark. The laseroutput level and other conditions of the laser are prescribed for Simirror wafers not to cause splash of particles. Therefore, in themarking on an SOI wafer according to the above SEMI standard, particlesare generated and a dot diameter changes in some cases due to itsmultilayer structure and the action of a heat-accumulating layer ofSiO₂.

[0017] In the case of deep mark, change of dot diameter is moreseriously. FIG. 23 shows schematically this state. For example, in thecase where a laser beam is projected onto an SOI wafer having an SOIlayer of 100 to 200 nm thick, a buried insulating layer of 100 to 200 nmthick under the same laser irradiation conditions as in the case of FIG.18, the diameter X1 of the inner protruded portion is about 0.045 mm,the diameter X2 of the recessed portion is about 0.04 mm, the distanceX3 between the inner protruded portion and the outer protruded portionranges from 0.02 to 0.03 mm, the depth Y1 of the recessed portion rangesfrom 2.5 to 3.0 μm, the height Y2 of the inner protruded portion rangesfrom 1.0 to 1.5 μm, and the height Y3 of the outer protruded portionranges from 0.8 to 1.5 μm. Incidentally, the depth Y1 of the recessedportion, and the heights Y2 and Y3 are indicated as approximate values.

[0018] In formation of the mark on the SOI layer surface, it is observedthat the recessed portion constituting marked characters becomes boldand particles 25 are splashed around the characters, as shown in FIG.23. The conditions of not causing the splashing of particles depend onthe SOI layer structure and the thickness of the respective layers, sothat the setting conditions therefor are complicated and laborious.Furthermore, when the laser has a lower output level that the particlesplashing is retarded, the depth of the recessed portion formed by thelaser irradiation becomes smaller, thereby rendering the reading of themark difficult.

SUMMARY OF THE INVENTION

[0019] An object of the present invention is to provide a semiconductorsubstrate which has a readable mark and can be easily marked withoutcausing deposition of splashed particles, and to provide also a processfor producing the semiconductor substrate.

[0020] According to an aspect of the present invention, there isprovided a semiconductor substrate having a semiconductor layer formedon a supporting substrate with interposition of an insulating layertherebetween, wherein a mark is formed on a region other than a surfaceregion of the semiconductor layer.

[0021] According to another aspect of the present invention, there isprovided a process for producing a semiconductor substrate having asemiconductor layer formed on a supporting substrate with interpositionof an insulating layer therebetween, the process comprising a step offorming a mark on a region other than a surface region of thesemiconductor layer.

[0022] According to still another aspect of the present invention, thereis provided a semiconductor substrate having a semiconductor layerformed on a supporting substrate with interposition of at least onelayer therebetween, wherein a mark is formed on a region other than asurface region of the semiconductor layer.

[0023] According to a further aspect of the present invention, there isprovided a process for producing a semiconductor substrate having asemiconductor layer formed on a supporting substrate with interpositionof at least one layer therebetween, the process comprising a step offorming a mark on a region other than a surface region of thesemiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1 is a top view of a part of a semiconductor substrateaccording to an embodiment of the present invention.

[0025]FIG. 2 is a sectional view of a part of a semiconductor substrateaccording to an embodiment of the present invention.

[0026]FIG. 3 is a top view of a part of another semiconductor substrateaccording to an embodiment of the present invention.

[0027]FIG. 4 is a sectional view of a part of another semiconductorsubstrate according to an embodiment of the present invention.

[0028]FIG. 5 is a top view of a part of a semiconductor substrateaccording to an embodiment of the present invention.

[0029]FIG. 6 is a sectional view of a part of a semiconductor substrateaccording to an embodiment of the present invention.

[0030]FIG. 7 is a sectional view of a part of bonded substratesaccording to an embodiment of the present invention.

[0031]FIGS. 8A, 8B, 8C, 8D, 8E and 8F are sectional views explainingproduction steps of a semiconductor substrate according to an embodimentof the present invention.

[0032]FIG. 9 is a flow chart of production steps of a semiconductorsubstrate according to an embodiment of the present invention.

[0033]FIG. 10 is a flow chart of production steps of a semiconductorsubstrate according to an embodiment of the present invention.

[0034]FIG. 11 is a flow chart of production steps of a semiconductorsubstrate according to an embodiment of the present invention.

[0035]FIG. 12 is a flow chart of production steps of a semiconductorsubstrate according to an embodiment of the present invention.

[0036]FIGS. 13A, 13B, 13C, 13D, 13E and 13F are sectional viewsexplaining production steps of a semiconductor substrate according to anembodiment of the present invention.

[0037]FIGS. 14A, 14B, 14C, 14D and 14E are sectional views explaining aproduction steps of a semiconductor substrate according to an embodimentof the present invention.

[0038]FIG. 15 is a flow chart of production steps of a semiconductorsubstrate according to an embodiment of the present invention.

[0039]FIG. 16 is a flow chart of production steps of a semiconductorsubstrate according to an embodiment of the present invention.

[0040]FIG. 17 is a flow chart of production steps of a semiconductorsubstrate according to an embodiment of the present invention.

[0041]FIG. 18 is a cross-sectional view showing the shape of a lasermark.

[0042]FIG. 19 is a top view of a part of a semiconductor substrate.

[0043]FIG. 20 is a cross-sectional view of a part of a semiconductorsubstrate.

[0044]FIG. 21 is a top view of a part of an SOI substrate.

[0045]FIG. 22 is a cross-sectional view of a part of an SOI substrate.

[0046]FIG. 23 is a cross-sectional view showing the shape of a lasermark.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] I. Constitution of Semiconductor Substrate

[0048] Embodiments of the semiconductor substrate according to thepresent invention is described below.

Embodiment 1

[0049]FIG. 1 is a top view of a part of a semiconductor substrateaccording to the present invention. FIG. 2 is a cross-sectional view ofthe semiconductor substrate taken along the line 2-2 of FIG. 1.

[0050] An SOI substrate is constituted of a supporting substrate 1 suchas a single-crystalline silicon wafer, a buried insulating layer 2 suchas of silicon oxide, and a semiconductor layer (SOI layer) 3 such as asingle-crystalline silicon layer.

[0051] In a surface region 5 of the semiconductor layer 3, asemiconductor device for an integrated circuit and the like is formed. Amark 4 is formed in a region 6 which is a nearly flat region of thesurface of peripheral region 13 of the semiconductor substrate. Thesubstrate has a notch 12.

[0052] The edge of the surface region 5 of the SOI layer 3 (i.e., insideborder line of the peripheral region) is indicated by the circle of aradius R2. The outer peripheral edge (outside border line of theperipheral region) of the substrate is indicated by the circle of aradius R1. The region between the circle of the radius R2 and the circleof the radius R1 is the peripheral region 13.

[0053] In more detail, general SOI wafers available at present usuallyhave a region having a width of several millimeters inward from theouter peripheral edge of the wafer, in which a device is not formed.This region is called “edge exclusion”.

[0054] In a SIMOX, for example, the SOI layer in the region having awidth of several millimeters inward from the outer peripheral edge mayhave a thickness of an off-specification or other detects caused by thenonuniformity of ion implantation.

[0055] In a bonding SOI wafer, a region having a width of severalmillimeters from the outer peripheral edge of a wafer is not bondedowing to sagging of the peripheral portion of an original wafer as astarting material, whereby the region has no SOI structure. Further,since the edge line of the SOI layer is not smooth, patterning issometimes conducted to remove a part of the SOI layer to bringartificially the edge thereof inward.

[0056] In marking on such an SOI wafer, the mark should be formed on aregion having no SOI structure. Therefore, on bonded wafers having noSOI layer in the peripheral region, the marking is conducted on theperipheral region 13 as shown in FIGS. 1 and 2. This method isadvantageous in that the marking can be conducted in a less number ofthe steps and that the number of the chips obtainable in the SOI regionis not decreased, in comparison with the SOI layer removal method.

Embodiment 2

[0057]FIG. 3 is a top view of a part of a semiconductor substrateaccording to the present invention. FIG. 4 is a cross-sectional view ofthe semiconductor substrate taken along the line 4-4 of FIG. 3.

[0058] A semiconductor layer (SOI layer) 3 and a insulating layer 2 arepartially hollowed and removed to form an exposed region 14, where apart of the supporting substrate 1 is exposed, inside the edge of thesemiconductor layer 3, namely on a region (internal region) excludingthe peripheral region 13 from the supporting substrate 1.

[0059] The mark 4 is made on this exposed region 14. Although in FIG. 3the mark 4 is constituted of alphabets, the mark 4 may be a bar code, anumeral, a character, a symbol, or combination thereof.

[0060] The edge (inside border line of the peripheral region) of thesurface region 5 of the SOI layer 3 is shown by a circle line of radiusR2. The outer peripheral edge (outside border line of the peripheralregion) of the substrate is shown by the circle of a radius R1. In thisEmbodiment, the mark is formed inside the circle of a radius R2.

[0061] The semiconductor substrate according to this Embodiment isproduced through the steps of preparing a semiconductor substrate suchas an SOI wafer, masking the semiconductor substrate except the regionfor formation of the exposed region 14, removing the portion of thesemiconductor layer 3 from the region not masked for exposed regionformation by etching or the like, removing the underlying insulatinglayer 2 by etching or the like to expose the surface of thesemiconductor, and forming a mark by laser irradiation or the like onthe exposed region 14, whereby an SOI substrate is obtained as shown inFIGS. 3 and 4.

Embodiment 3

[0062] In this Embodiment, the mark is formed on the back surface of thesupporting substrate.

[0063] In this Embodiment, the mark is formed on the back surface of asupporting substrate of the SOI substrate in the same manner as themarking on the front surface of a mirror wafer as shown in FIGS. 19 and20.

[0064] Since the mark is made on the back surface of the supportingsubstrate, the effective area of the SOI layer on the front surface ofthe supporting substrate is not decreased.

Embodiment 4

[0065]FIGS. 5 and 6 illustrate the structure of the peripheral regionmarked and its vicinity in a semiconductor substrate.

[0066]FIG. 5 is a top view of the peripheral region and its vicinity.FIG. 6 is a sectional view of the peripheral region and its thevicinity.

[0067] Numeral 34 denotes an edge of a buried insulating layer 2.Numeral 35 denotes an edge of SOI layer 3. In this Embodiment, the edge34 of the insulating layer 2 is extended to the outside of the edge 35of the SOI layer 3. Thereby, under-etching of the insulating layer 2 bycleaning or the like with a cleaning solution having an etching propertycan be prevented to retard chipping of the SOI layer. However, this isnot essential. More preferably, the corner of the SOI layer 3 or of theburied insulating layer 2 may be worked to round it off or to make theangle obtuse.

[0068] The mark 4 is formed in an outer part in the peripheral region13. In FIG. 5, the mark 4 is made outside an imaginary line 33′.

[0069] The imaginary line 33′ is explained by reference to FIG. 7. FIG.7 is a sectional view of bonded substrates produced by bonding twosubstrate for preparing a bonding SOI substrate. In FIG. 7, the mark 4is made outside the position indicated by the numeral 33. The mark 4 isformed on a flat surface of the peripheral region 13. The flat surfaceis not contacted with the wafer 30. A part of the mark 4 may be formedon a bevelled surface of the peripheral region. In the bonded state ofthe two substrates, the edge of the bonding interface is at the positionindicated by the numeral 32, which position is called “contact edge”.Thereafter, the bonded substrates are heat-treated (or bonding-annealed)to increase the bonding strength of the substrates, whereby the edge ofthe bonding interface moves outward to the position indicated by thenumeral 33 to increase the area of the bonding interface.

[0070] Later, the unnecessary portion of the substrate 30 is removed tomake the substrate 30 thinner to obtain the SOI substrate. On thesurface of the supporting substrate 1 of the resulting SOI substrate,the original position of the bonding edge 33 is indicated by theimaginary line 33′, and the original position of the contact edge 32 isindicated by the imaginary line 32′.

[0071] Numeral 31 shows an intended position corresponding to the edge35 of the completed SOI layer 3. The distance L31 from the outerperipheral edge of the supporting substrate 1 is preferably not morethan 3 mm, more preferably as small as possible in a range of 3 mm orless.

[0072] The position of the contact edge 32 is determined depending onthe shape of the outer peripheral portion of the used substrates 1 and30 after beveling: the distance L32 between the outer peripheral edge ofthe supporting substrate 1 and the contact edge 32 varies depending onthe beveled shape of the outer peripheral portion. Similarly the bondingedge 33 is shifted slightly.

[0073] If roughness or a foreign particle is present in the vicinity ofthe contact edge 32 of the substrate-bonding face, the bonding isdifficultly carried out in the vicinity to cause slight inward shiftingof the contact edge 32 as well as of the bonding edge 33. In such acase, the edge of the strongly bonded region is moved inward, whichforces the edge 35 of the SOI layer 3 to move inward to a position wherea sufficient bonding strength can be achieved, thereby preventingshortening of the distance L31.

[0074] The mark in the present invention can be formed at a portionbetween the outer peripheral edge of the supporting substrate and theedge of the SOI layer, more preferably outside the position 32′corresponding to the contact edge 32. Also preferably, the mark isformed outside the position 33′ corresponding to the bonding edge 33.

[0075] Preferably also, only the portion of the bonding edge 33 or thecontact edge 32 for mark formation is moved inward locally and the markis made thereon without decreasing the effective area of the SOI layer.

[0076] Embodiments of the semiconductor substrate according to thepresent invention are explained above. The present invention is notlimited thereto, and includes substitution of the constituting elementto an equivalent provided that the objects of the present invention canbe achieved.

[0077] The supporting substrate useful in the present invention may be asemiconductor substrate of Si, Ge, SiC, GaAs, GaAlAs, GaN, InP, or thelike, but is not limited thereto, provided that a mark can be formed onthe surface thereof.

[0078] The insulating layer useful in the present invention may becomposed of at least one of silicon oxide, silicon nitride, siliconoxide nitride, and the like. The insulating layer may be constituted ofa single layer or a lamination of plural layers. The thickness of theinsulating layer may be in the range from 1 nm to 10 μm.

[0079] The semiconductor layer useful in the present invention is formedfrom at least one semiconductor including Si, Ge, SiC, GaAs, GaAlAs,GaN, InP and the like. The semiconductor layer may be of a single layeror a lamination of plural layers. The thickness of the semiconductorlayer may be in the range from 1 nm to 10 μm.

[0080] The shape of the semiconductor substrate of the present inventionis not limited to the notched wafer as shown in FIG. 1, but may be othershape of a wafer such as a wafer having an orientation flat. The SOIsubstrate for use in the present invention may be a nonbonding substratesuch as a SIMOX wafer, but is preferably a bonding SOI substrate.

[0081] The region for the marking may be near the notch or theorientation flat, or at the position opposing thereto, or may be at anyother position.

[0082] The mark is formed in the peripheral region as mentioned above.Preferably, the mark is formed therein on a flat portion or slightlyinclined portion formed by beveling. Otherwise, the mark may be formedon a portion exposed by partial removal of the semiconductor layer.

[0083] The marking can be conducted by Nd:YAG laser, CO₂ lager, or thelike, or by use of a diamond pen.

[0084] The mark may be constituted of at least one of numerals,characters, symbols, and bar codes, and the like, or combinationthereof. The characters include alphabet, Japanese kana, and Greekcharacters.

[0085] For a special use, the SEMI standard need not be applied. Thenumerals, characters, symbols, and the like for constituting the markmay be arranged in a line or in a curve along the outer peripheral edgeof the wafer. In the case where the peripheral region formed by removalof the semiconductor layer is narrow, or where the number of digits ofthe mark is large, the mark is preferably arranged in a curve along theouter peripheral edge not to interfere the SOI layer.

[0086] The marked wafers may be packed up and shipped without furthertreatment, or may be packed up after washing or inspection and shipped.Otherwise, the marked wafers may be introduced to a device productionstep without treatment or after cleaning or inspection.

[0087] II. Process for Producing Semiconductor Substrate

[0088] Embodiments of the process is described below for producing theabove semiconductor substrate according to the present invention.

[0089] The process for producing the semiconductor substrate accordingto the present invention comprises the steps of preparing asemiconductor substrate having a semiconductor layer formed on asupporting substrate with interposition of an insulating layertherebetween, and forming a mark on a region other than the surfaceregion of the semiconductor layer.

[0090] The semiconductor substrate useful in the present invention isdescribed above. The preferred semiconductor substrate includesnonbonding SOI substrates having an insulating layer formed by oxygenand/or nitrogen ion implantation and heat treatment; bonding SOIsubstrates produced by ion-implanting hydrogen and/or inert gas onto afirst substrate, bonding the first substrate to a second substrate as asupporting substrate, and separating the bonded substrates at aseparation layer having been formed by the above ion implantation; andbonding SOI substrates having a semiconductor layer formed bytransferring a nonporous semiconductor layer formed on a porous layeronto a supporting substrate.

[0091] Another process for producing the semiconductor substrateaccording to the present invention comprises a step of marking on asupporting substrate such as a so-called handle wafer before formationof an SOI structure.

Embodiment 5

[0092] A process for producing a semiconductor substrate is explainedwith reference to FIGS. 8A to 8F and 9.

[0093] A first substrate 30 such as a single-crystalline silicon waferis anodized to form a porous layer 37 such as a porous silicon layer onthe surface. Further, if necessary, the inside wall of the pores of theporous silicon is thermally oxidized to form a protective silicon oxidefilm. Then the openings on the surface of the porous layer 37 are sealedby heat treatment in a hydrogen atmosphere.

[0094] On the porous layer 37, a nonporous semiconductor layer 38 suchas a single-crystalline silicon layer is formed by epitaxial growth byCVD or the like. This semiconductor 38 layer is a layer to betransferred, that is, becomes a transferred layer. Further, ifnecessary, an insulating layer 39 is formed by thermal oxidation of thefirst substrate 30. Thus a structure as shown in FIG. 8A is producedthrough the steps S11 and S12 in FIG. 9.

[0095] Then a second substrate such as a single-crystalline siliconwafer is prepared in the step S21. Marking is conducted on the surfaceof the peripheral portion thereof in the step S22. If necessary, thesurface of the second substrate may be thermally oxidized to form aninsulating layer. Otherwise, the marking may be made on the back surfaceof the second substrate at its any position. Primary process forproducing a single-crystalline silicon wafer comprises the steps ofslicing a silicon ingot, lapping, etching and polishing. Deep mark isformed prior to lapping or etching. Shallow mark is formed prior topolishing.

[0096] The two substrates are bonded together in the step S13 as shownin FIG. 8B. The strength of the bonding may be increased by heattreatment in an oxidative atmosphere or the like. In the case where themarking is conducted on the front surface, the mark is preferably formedoutside the contact edge or outside the bonding edge in the step S13.

[0097] In the step S14, the unnecessary portion of the first substrateis removed. Specifically, as shown in FIG. 8C, the nonporous portion 36of the back surface side of the first substrate is removed from thebonded substrates by at least one of the methods of grinding, polishing,etching, and separation. Then, the porous layer 37 remaining on thesurface (formerly the back surface) of the semiconductor 38 bonded tothe second substrate is removed by polishing, etching, or hydrogenannealing, or is made nonporous. Thus the transfer of the semiconductorlayer 38 is completed.

[0098] In the step S15, the peripheral portion of the SOI substrate isformed. Specifically, as shown in FIG. 8E, the exposed surface of thesemiconductor layer 38 is covered by an etching mask of a sealingmaterial, photoresist, or the like. Then the peripheral portion of thesemiconductor layer 38 is removed by etching so that the edge of thesemiconductor layer 38 for forming the SOI layer is brought to theposition 31 shown in FIGS. 5 to 7. Further, the peripheral portion ofthe insulating layer 39 is also removed by etching or polishing.

[0099] In such a manner, an SOI substrate is prepared as shown in FIG.8F. The mark on the SOI substrate is formed at the position shown inFIGS. 1, 2, 5 and 6.

Embodiment 6

[0100] Another process for producing a semiconductor substrate isexplained with reference to FIG. 10.

[0101] This Embodiment is different from the above Embodiment 5 in thatthe marking is conducted between the steps of removing unnecessaryportions of the first substrate.

[0102] In the same manner as in Embodiment 5, a first substrate afterthe steps S11 and S12 is bonded to an unmarked second substrate (StepS13).

[0103] In the step S14, a part of the unnecessary portions of the firstsubstrate is removed. Specifically, as shown in FIG. 8C, the nonporousportion 36 on the back surface side of the first substrate is removed byat least one of the methods of grinding, polishing, etching, andseparation.

[0104] Then in the step S15, the marking is conducted at the peripheralportion of the front surface side of the second substrate. Even ifforeign matters splashed by the marking deposit onto the front surfaceof the second substrate, the splashed matters are removed from the frontsurface in the subsequent step of removing the porous layer 37.Therefore, the surface region of the semiconductor layer for forming theSOI layer is not soiled with the foreign matter. Otherwise, the markingmay be conducted on the back surface side of the second substrate.

[0105] In the subsequent step of S16, the porous layer 37 remaining onthe surface (formerly the back surface) of the semiconductor layer 38bonded to the second substrate is removed by polishing, etching, orhydrogen annealing, or is made nonporous. Thus the transfer of thesemiconductor layer 38 is completed.

[0106] Then in the step S17, the peripheral portion of the SOI substrateis formed.

[0107] In such a manner, an SOI substrate is obtained as shown in FIG.8F. The mark on the SOI substrate is formed at the position as shown inFIGS. 1, 2, 5 and 6.

Embodiment 7

[0108] Still another process for producing a semiconductor substrate isexplained with reference to FIG. 11.

[0109] This Embodiment is different from the above Embodiment 5 in thatthe marking is conducted after the step of removing unnecessary portionsof the first substrate and before the step of formation of peripheralportion.

[0110] In the same manner as in Embodiment 5, a first substrate afterthe steps S11 and S12 is bonded to an unmarked second substrate (StepS13).

[0111] In the step S14, a part of the unnecessary portion of the firstsubstrate is removed. Specifically, as shown in FIG. 8C, the nonporousportion 36 on the back surface side of the first substrate is removed bythe methods of grinding, polishing, etching, separation, or the like.Then, as shown in FIG. 8D, the porous layer 37 remaining on the surface(formerly the back surface) of the semiconductor layer 38 bonded to thesecond substrate is removed by polishing, etching, or hydrogenannealing, or is made nonporous. Thus the transfer of the semiconductorlayer 38 is completed.

[0112] In some cases in the above-mentioned separation of the nonporousportion, the interface between the porous layer and the semiconductorlayer 38 may be cracked, thereby allowing the porous layer to beseparated together with the nonporous portion from the semiconductorlayer 38. After this separation, in some cases, there is no remainingporous layer on the semiconductor layer 38.

[0113] Then, in the step S15, the marking is conducted at the peripheralportion of the front surface side of the second substrate with a mask MKcovering the surface region of the semiconductor 38, as shown in FIG.8E. In the marking, even if foreign matters splashed by the markingoperation deposit onto the front surface of the second substrate, thesplashed matters are removed in the subsequent step of removing the maskMK from the front surface side. Therefore, the surface region of thesemiconductor layer for forming the SOI layer is not soiled by foreignmatters. Otherwise, the marking may be conducted on the back surfaceside of the second substrate.

[0114] In the subsequent step S16, the peripheral portion of the SOIsubstrate is formed using the mask MK.

[0115] In such a manner, an SOI substrate is obtained as shown in FIG.8F. The mark on the SOI substrate is formed at the position as shown inFIGS. 1, 2, 5 and 6.

Embodiment 8

[0116] A further process for producing a semiconductor substrate isexplained with reference to FIG. 12.

[0117] This Embodiment is different from the above Embodiment 7 in thatthe marking is conducted after formation of the peripheral portion withthe mask MK kept covering in the same manner as in Embodiment 7 andwithout peeling the mask MK.

[0118] Thus in this Embodiment, an SOI substrate is also prepared asshown in FIG. 8F. The mark on the SOI substrate is formed at theposition shown in FIGS. 1, 2, 5 and 6.

Embodiment 9

[0119] A process for producing a bonding semiconductor substrate isexplained which employs an ion-implanted layer as a separation layer,with reference to FIGS. 13A to 13F.

[0120] A first substrate 30 such as a single-crystalline silicon waferis thermally oxidized at the surface to form an insulating layer 39 suchas a silicon oxide layer. Thereto, inert gas ions such as hydrogen ions,helium ions, and neon ions are implanted to a predetermined depth toform an ion-implanted layer 40 where the concentration of the implantedions is locally high. The portion positioned on the ion-implanted layer40 is a layer to be transferred, that is, becomes a transferred layer.FIG. 13A shows the structure of the first substrate 30 thus obtained.

[0121] Separately, a second substrate such as a single-crystalline waferis prepared. A marking is conducted on the peripheral portion of thefront surface, or the marking may be conducted on the back surface sideof the second substrate.

[0122] The first substrate and the second substrate are bonded togetherso that the semiconductor layer 38 is placed inside, thereby obtaining astructure as shown in FIG. 13B.

[0123] The bonded substrates are then heat-treated at a temperatureranging from 400 to 600° C. or higher to increase the bonding strengthand simultaneously cause cracking in the ion-implanted layer 40. Therebythe portion 36 of the first substrate comes off from the bondedsubstrates, and the semiconductor layer 38 is transferred onto thesecond substrate as shown in FIG. 13C.

[0124] The exposed separation surface of the semiconductor layer 38 ispolished. In this step, the peripheral portions of the layers 38 and 39may be removed simultaneously to obtain the structure shown in FIG. 13D.Otherwise, hydrogen annealing may be conducted instead of the polishing,or the polishing and the hydrogen annealing are successively conducted.It is preferable that annealing for enhancing bonding strength isperformed prior to polishing or subsequent to polishing.

[0125] Then, the peripheral portion of the SOI substrate is formed.Specifically, as shown in FIG. 13E, the exposed surface of thesemiconductor layer 38 is covered by an etching mask MK made of asealing material, photoresist, or the like. The peripheral portion ofthe semiconductor layer 38 is removed by etching so that the edge of thesemiconductor layer 38 for forming the SOI layer is brought to theposition 31 shown in FIGS. 5 to 7. Further, the peripheral portion ofthe insulating layer 39 is also removed by etching or polishing.

[0126] In such a manner, an SOI substrate is obtained as shown in FIG.13F. The mark on the SOI substrate is formed at the position as shown inFIGS. 1, 2, 5 and 6.

[0127] After the step of FIG. 13C, the step of FIG. 13E may be conductedby omitting the step of FIG. 13D.

Embodiment 10

[0128] This Embodiment is conducted in the same manner as in Embodiment9 except that the timing of the marking is changed, that is, the markingis conducted in a peripheral region on the front surface of thesupporting substrate with using the mask MK in the covering state asshown in FIG. 13E before removal of the peripheral portion of thesemiconductor layer 38.

[0129] Thus an SOI substrate is obtained as shown in FIG. 13F. The markon the SOI substrate is formed at the position as shown in FIGS. 1, 2, 5and 6. Otherwise the marking may be conducted on the back surface of thesupporting substrate. In the case that polishing or cleaning can removeparticles generated by marking, masking step is not required.

Embodiment 11

[0130] This Embodiment is conducted in the same manner as in Embodiment9 except that the timing of the marking is changed, that is, the markingis conducted in a peripheral region on the front surface of thesupporting substrate with using the mask MK in the covering state asshown in FIG. 13E after removal of the peripheral portion of thesemiconductor layer 38 before removal of the mask MK.

[0131] Thus an SOI substrate is obtained as shown in FIG. 13F. The markon the SOI substrate is formed at the position as shown in FIGS. 1, 2, 5and 6. Otherwise the marking may be conducted on the back surface of thesupporting substrate.

Embodiment 12

[0132] A process of producing a semiconductor substrate with anon-bonding method is explained with reference to FIGS. 14A to 14E and15.

[0133] In the step S11 of FIG. 15, a semiconductor substrate 1 such as asingle-crystalline wafer is prepared as shown in FIG. 14A.

[0134] In the step S12 of FIG. 15, the marking is conducted on theperipheral region on the front surface side of the semiconductorsubstrate. Otherwise, the marking may be conducted on the back surfaceside of the semiconductor substrate.

[0135] Then, the surface of the semiconductor substrate 1 is thermallyoxidized to form an insulating layer 41 such as a silicon oxide layer,as shown in FIG. 14B.

[0136] In the step S13 of FIG. 15, insulator-forming ions such as oxygenions are implanted to a predetermined depth to form an ion-implantedlayer where the concentration of the implanted ions is locally high.This substrate is heat-treated to form a buried insulating layer 2composed of a compound of the implanted oxygen and silicon. The portionof the semiconductor layer 3 on this insulating layer 2 becomes an SOIlayer. The resulting SOI substrate has a structure as shown in FIG. 14C.

[0137] In the step S14 of FIG. 15, the unnecessary portion of theinsulating layer 41 at least on the surface side of the SOI layer isremoved to obtain a marked SOI substrate. When the marking is conductedon the front side surface, the marked portion is also made to have theSOI structure having recessed and protruded portions by the ionimplantation and the heat treatment after the marking, thereby enablingidentification of the mark from the front surface side. In this case,the step of FIG. 14D need not be conducted.

[0138] As a modification of this Embodiment, the ion implantation may beconducted in a region excluding the marked portion to form a markedportion not having the SOI structure on the peripheral portion of thefront surface side.

Embodiment 13

[0139] A process of producing a semiconductor substrate is explainedwith reference to FIGS. 14A to 14E and 16. This Embodiment is conductedin the same manner as in Embodiment 12 except that the timing of themarking is changed.

[0140] In the step S11 of FIG. 16, a semiconductor substrate 1 such as asingle-crystalline wafer is prepared as shown in FIG. 14A.

[0141] Then, the surface of the semiconductor substrate 1 is thermallyoxidized to form an insulating layer 41 such as a silicon oxide layer asshown in FIG. 14B.

[0142] In the step S12 of FIG. 16, insulator-forming ions such as oxygenions are implanted to the substrate in a predetermined depth to form anion-implanted layer where the concentration of the implanted ions islocally high. This substrate is heat-treated to form a buried insulatinglayer 2 composed of a compound consisting of the implanted oxygen andsilicon. The semiconductor layer 3 positioned on this insulating layer 2becomes an SOI layer. The resulting SOI substrate has a structure asshown in FIG. 14C.

[0143] In the step S13 of FIG. 16, as shown in FIG. 14D, a mask MK isapplied and, if necessary, the insulating layer 41 is removed, and themarking is conducted. The mark is formed such that the recessed portionof the mark reaches the lower portion of the insulating layer 2 throughthe semiconductor layer 3.

[0144] In the step S14 of FIG. 16, the mask MK and unnecessaryinsulating layer 41 are removed to obtain an SOI substrate as shown inFIG. 14E.

[0145] In this Embodiment, since the SOI layer is protected by the mask,even when splash of the particles is caused by laser marking, thesoiling by splash of the particles can be prevented.

Embodiment 14

[0146] A process of producing a semiconductor substrate is explainedwith reference to FIG. 17. This Embodiment is conducted in the samemanner as in Embodiment 13 except that the timing of the marking ischanged.

[0147] The steps S11 and S12 of FIG. 17 are conducted in the same manneras in Embodiment 13.

[0148] In the step S13 of FIG. 17, the unnecessary insulating layer 41is removed from the semiconductor as shown in FIG. 14E to obtain an SOIsubstrate.

[0149] In the step S14 of FIG. 17, the surface region of thesemiconductor layer is covered with a mask, and the marking is conductedin the peripheral region on the front surface side of the SOI substrate.The mark is formed such that the recessed portion of the mark reachesthe lower portion of the insulating layer 2 through the semiconductorlayer 3.

[0150] In this Embodiment, since the SOI layer is protected by the mask,even when splash of the particles is caused by laser marking, thesoiling by splash of the particles can be prevented.

Embodiment 15

[0151] A process of production of a bonding semiconductor substrate isexplained with reference to FIGS. 8A to 8F.

[0152] A single-crystalline substrate of a P-type or N-type having aspecific resistance of 0.01 Ω·cm is prepared as a first substrate. Thissubstrate is anodized in an HF-containing solution to form a porouslayer 37 as a separation layer.

[0153] The anodization conditions for forming the porous layer 37consisting of porous silicon as a single layer are exemplified as below:

[0154] Current density: 7 (mA·cm⁻²)

[0155] Anodization solution:

[0156] Hydrofluoric acid:water:ethanol=1:1:1

[0157] Time: 11 (minutes)

[0158] Porous layer thickness: 12 (μm)

[0159] The thickness of the porous layer can be varied in the range fromseveral hundred μm to about 0.1 μm by adjusting the anodization time.

[0160] In formation of porous layer constituted of plural porous siliconlayers, the first step and the second step of the anodization may beconducted under the conditions as below:

[0161] First step

[0162] Current density: 7 (mA·cm⁻²)

[0163] Anodization solution:

[0164] Hydrofluoric acid:water:ethanol=1:1:1

[0165] Time: 5 (minutes)

[0166] First porous layer thickness: 5.5 (μm)

[0167] Second step

[0168] Current density: 30 (mA·cm⁻²)

[0169] Anodization solution:

[0170] Hydrofluoric acid:water:ethanol=1:1:1

[0171] Time: 10 (seconds)

[0172] Second porous layer thickness: 0.2 (μm)

[0173] The first porous silicon layer formed firstly as the surfacelayer by anodization at a lower current density is employed forformation of a high-quality epitaxial Si layer, and the second poroussilicon layer formed secondly as the lower layer by anodization at ahigher current density is employed for facilitating the separation, thetwo porous layers having different functions. Therefore, the thicknessof the porous Si layer formed is not limited to the above, but may rangefrom several hundred μm to about 0.1 μm. In addition to the above twolayers, third layer or more layers may be formed thereon.

[0174] This substrate is oxidized at 300 to 600° C. in an oxygenatmosphere to cover the inside walls of the holes of the porous siliconwith a protection film composed of a thermal oxidation film. The surfaceof the porous layer 37 is treated with hydrofluoric acid to remove onlythe oxide film on the surface of the porous layer 37 while the oxidefilm on the inside walls of the holes is kept unremoved. On the poroussilicon, single-crystalline silicon is grown epitaxially by CVD(chemical vapor deposition). The growth conditions are shown below.Source gas: SiH₂Cl₂/H₂ Gas flow rate: 0.5/180 L/min Gas pressure: 1.1 ×10⁴ Pa (about 80 Torr) Temperature: 950° C. Growth rate: 0.3 μm/min

[0175] Prior to the epitaxial growth, the porous layer 37 isheat-treated (prebaked) in a hydrogen atmosphere in the epitaxial growthchamber. This heat treatment is necessary for improving the quality ofthe crystal of an epitaxial growth layer 38. Actually, the crystaldefects of the epitaxial growth layer 38 can be decreased to not morethan 10⁴ cm⁻². The resulting epitaxial growth layer 38 is employed lateras the transferred layer.

[0176] On the surface of this epitaxial growth layer, an SiO₂ layer of20 nm to 2 μm thick is formed as an insulating layer 39 by thermaloxidation. Thus the structure is obtained as shown in FIG. 8A.

[0177] The surface of the insulating layer 39 and a surface of aseparately prepared second Si substrate are brought into contact witheach other, and the contacted substrates are heat-treated at atemperature of 1100° C. for 2 hours to cause bonding of the substrates,whereby the structure as shown in FIG. 8B is obtained.

[0178] From the resulting multilayered structure, the porous layer 37 isremoved to obtain an SOI substrate which comprises the second substrate1 and the epitaxial growth layer 38 transferred thereon. For this, theportion 36 of the first Si substrate is removed by grinding, polishing,etching or the like to expose the porous layer 37, and then the porouslayer 37 is removed by etching. Otherwise, the multilayered structure isseparated at the porous layer 37, and if the porous portion remains onthe separation face of the epitaxial growth layer 38 transferred ontothe second substrate 1, the porous portion is removed by etching,hydrogen annealing or the like.

[0179] The substrate separation method includes a method of inserting awedge between the substrates; a method of pulling the substratesopposite; a method of applying a shearing force; a method of utilizingthe effect of a fluid wedge such as water jet, gas jet, and staticpressure fluid; a method of applying ultrasonic wave; a method ofapplying a thermal stress by heating and cooling. Thus a structure isobtained as shown in FIG. 8C.

[0180] Thereafter, the porous Si layer 37 remaining on the secondsubstrate 1 is selectively etched by a liquid mixture composed ofhydrofluoric acid, hydrogen peroxide and water. The semiconductor layer38 composed of nonporous single-crystalline silicon remains unetched.This layer 38 functions as an etch-stopping material, thereby allowingcomplete removal of the porous Si by selective etching. Thus a structureis obtained as shown in FIG. 8D.

[0181] The etching rate of the nonporous Si single-crystal in theabove-mentioned etching liquid mixture is extremely low: the selectivityratio of etching rate of a porous layer relative to the etching rate ofa nonporous layer reaches as high as 10⁵ or more, and therefore thethickness decrease of the nonporous layer by etching (about several tenangstroms) is negligible practically.

[0182] Thus the semiconductor layer 38 of 0.2 μm thick constituted ofsingle-crystalline Si is formed on the insulating layer 39. Thesingle-crystalline Si layer does not change at all by the selectiveetching of the porous Si. The thickness of the formed semiconductorlayer 38 had uniformity in the range of 201 nm ±4 nm in measurement at100 points over the entire surface.

[0183] No additional crystal defect is observed in the Si layeraccording to transmission electron microscopy.

[0184] The surface can be made flat by heat treatment at 1100° C. in ahydrogen atmosphere.

[0185] The oxide film may be formed on the surface of the secondsubstrate, in place of the epitaxial growth layer, to obtain the sameresults.

[0186] A mask MK is applied to cover the surface region of thesemiconductor layer 38, and a part of the semiconductor layer 38 and apart of the insulating layer 39 on the peripheral region of 1 to 3 mmwide inward from the outer peripheral edge are removed by patterning tocorrect the shape of the peripheral portion. This treatment of peripherypatterning may be omitted.

[0187] On the peripheral region, near the notch or the orientation flatportion, a predetermined number of digits of alphanumeric characters,symbols, or bar cords are recorded by a laser marking apparatus. Therecorded characters need not meet the SEMI Standard. The size of thecharacter can be adjusted by about 0.8 mm-pitch with a usual lasermarking apparatus, and may be smaller, or larger for easy reading.

[0188] The aforementioned heat treatment in hydrogen atmosphere(hydrogen annealing) for surface flattening may be conducted after thislaser marking.

[0189] Thereafter, the mask MK is removed, and the SOI substrate iscleaned, inspected, packed up, and shipped.

[0190] The porous Si remaining on the side of the substrate portion 36of the first substrate is selectively etched with stirring in a liquidmixture of hydrofluoric acid, hydrogen peroxide and water. The surfaceof this etched substrate is subjected to hydrogen annealing, surfacepolishing, or a like treatment. The treated substrate can be reused asthe first substrate 30 or the second substrate 1.

Embodiment 16

[0191] A process for producing a bonding semiconductor substrate isexplained which employs an ion-implanted layer as a separation layer,with reference to FIGS. 13A to 13F.

[0192] On a first substrate 30 such as a single-crystalline Si wafer, aninsulating layer 39 composed of SiO₂ of 200 nm thick is formed bythermal oxidation.

[0193] Through the insulating surface layer 39, hydrogen cations areimplanted at a power level of 50 keV at a density of 5×10¹⁶ cm⁻². Thehydrogen ions may be replaced by ions of an inert gas such as helium.Thereby a structure is obtained as shown in FIG. 13A. The surface of theinsulating layer and the surface of a separately prepared secondsubstrate such as a single-crystalline Si wafer are brought insuperposition and contact with each other. Thereby a structure isobtained as shown in FIG. 13B.

[0194] The resulting structure is annealed at 600° C., whereby it isseparated into two pieces near the projection range of ion implantation(ion-implanted layer 40). The ion-implanted layer 40, which causes theseparation by heat treatment, is in a porous state. Therefore, theseparation surfaces are rough. At least, the surface of the side of thesecond substrate 1 is smoothened by polishing, or hydrogen annealing.Thereby, a structure is obtained as shown in FIG. 13C or 13D. It isprefer that bonding anneal is performed prior to smoothing step orsubsequent to smoothing step.

[0195] Thus the semiconductor layer 38 of 0.2 μm thick constituted ofsingle-crystalline Si is formed on the insulating layer 39. Thethickness of the formed semiconductor layer 38 had uniformity in therange of 201 nm±6 nm in thickness measurement at 100 points over theentire surface.

[0196] Further, a heat treatment is conducted at 1100° C. in a hydrogenatmosphere for one hour. By observation with an atomic force microscope,the surface roughness is about 0.2 nm in terms of mean square roughnessin a region of 50 μm square, which is comparable with an ordinarycommercial single-crystalline Si mirror wafer.

[0197] No additional crystal defect is observed in the semiconductorlayer 38 by transmission electron microscopy, and the excellentcrystallinity is confirmed to be maintained.

[0198] A mask MK is applied to cover the surface but to expose a part ofthe semiconductor layer 38 and a part of the insulating layer 39 in theperipheral region of 1 to 3 mm wide inward from the outer peripheraledge, and the exposed parts are removed by patterning to correct theshape of the peripheral portion as shown in FIG. 13F.

[0199] On the peripheral 3 mm-region, near the notch or the orientationflat portion, 12 digits of alphanumeric characters are recorded by alaser marking apparatus. As mentioned before, the mark may be a symbolor a bar code. In the marking operation, no particle is deposited on SOIwafer. The laser power therefor is adjusted to about 220 mW. A range oflaser power is adjusted depending on mark depth or mark size.

[0200] The size of the alphanumeric characters is selected to meet theaforementioned SEMI Standard. The size of the character can be adjustedby a 0.8 mm-pitch with a usual laser marking apparatus, and may besmaller, or larger for easy reading.

[0201] Thereafter, the mask MK is removed, and the SOI substrate iscleaned, inspected, packed up, and shipped. Optionally, smoothing stepis performed subsequent to marking step.

[0202] The ion-implanted layer remaining on the side of the substrateportion 36 of the first substrate is removed and the substrate surfaceis flattened at least by etching, polishing, or annealing. The treatedsubstrate is can be reused as the first substrate 30 or the secondsubstrate 1.

[0203] In a modification of this Embodiment, single-crystalline Si isepitaxially grown in a thickness of 0.50 μm preliminarily on the firstsubstrate by CVD. The growth conditions are as below. Source gas:SiH₂Cl₂/H₂ Gas flow rate: 0.5/180 L/min Gas pressure: 1.1 × 10⁴ Pa(about 80 Torr) Temperature: 950° C. Growth rate: 0.30 μm/min

[0204] For reuse of the first substrate, the wafer thickness decreasecan be compensated by epitaxial growth as above, which enablessemipermanent reuse of the substrate. That is, the second or laterepitaxial growth is conducted to supplement the lost thickness of thewafer, not 50 μm, and the ion-implanted layer is formed in theepitaxially grown layer.

[0205] Further, similarly as in Embodiment 16, after the ionimplantation, the separation of the bonded substrates is conducted byapplying an external force to allow cracking from the edge of the bondedsubstrates without heat treatment.

Embodiment 17

[0206] Production of a semiconductor substrate by a non-bonding methodis explained with reference to FIGS. 14A to 14E.

[0207] A first single-crystalline 8 inch CZ—Si wafer is prepared as thesubstrate 1. Thereon an oxide film 41 composed of SiO₂ is formed in athickness of 50 nm by thermal oxidation as shown in FIGS. 14A and 14B.This oxide film is provided to prevent roughening of the surface on ionimplantation. Therefore, this oxidation film may be omitted.

[0208] Through the oxide film 41 on the surface, O⁺ ions are implantedat a density of 4×10⁷ cm⁻² at a power level of 180 keV at a temperatureof 550° C. Thereby, an oxygen ion-implanted layer is formed with aconcentration peak in the vicinity of the interface between theepitaxial growth layer and the original substrate. Nitrogen ions may beimplanted in addition to or in place of the oxygen ions.

[0209] This substrate is heat-treated at 1350° C. in an atmosphere ofO₂(10%)/Ar for 4 hours to obtain an SOI substrate having an 300 nm SOIlayer/90 nm buried oxide film as shown in FIG. 14C.

[0210] Then, the substrate is further heat-treated at 1350° C. in anatmosphere of O₂(70%)/Ar for 4 hours to obtain an SOI wafer having an200 nm SOI layer/120 nm buried oxide film.

[0211] A mask MK is applied onto the surface of the semiconductor layer3 (FIG. 14D). The mask has an aperture of 2.8 mm wide and 18.5 mm longrepresented by an X-Y coordinate:

X: −9.25 mm to +9.25 mm

Y: +93.7 mm to +96.5 mm

[0212] taking the center of the wafer as the origin (0,0) with the notchof the substrate directed upward, for exposing the underlying supportingsubstrate. From the unmasked portion, a portion of the semiconductorlayer 3 and a portion of the insulating layer 2 are removed bypatterning-etching

[0213] With the mask kept covering the surface region of thesemiconductor layer 3, an ID code of 10 digits is recorded on therecording region by a laser marking apparatus. The laser power isadjusted to 220 mW, and the size of the alphanumerical characters isselected in accordance with the SEMI Standard. The size of the characteris adjustable by about 0.8 mm-pitch. The size may be smaller, or may belarger for ease of reading. The size of the region of the SOI structureremoval may be changed in accordance with the size of the recordedcharacter. In particular, when smaller characters are used, the regionof the SOI structure removal is made smaller to decrease the unusedremoval region and to increase the number of the produced chips. Forspecial uses, the substrate need not meet the SEMI Standard. The mask MKis removed, and the surface oxide film 41 is removed to obtain the SOIwafer in FIG. 14E, which may be further annealed in hydrogen.

[0214] Thereafter, the substrate is cleaned, inspected, packed up, andshipped.

[0215] The marking means applicable to the above-described embodimentsof the present invention includes lasers such as Nd:YAG laser, and CO₂laser; and use of a diamond pen. After formation of the mark, theprotruded portions formed in the marked region may be removed bygrinding or a suitable method at an appropriate time. In theembodiments, the particle removing step after marking enables to performmarking without mask. The particle removing step comprises at least oneof wet-cleaning, blush-cleaning, scrubbing, supersonic wave cleaning,polishing, or etching.

EXAMPLE 1

[0216] In a commercially available 8 inch SOI wafer, a part of thesemiconductor layer 3 and a part of the insulating layer 2 were removedby etching from the region represented by X-Y coordinate:

X: −9.25 mm to +9.25 mm

Y: +93.7 mm to +96.5 mm

[0217] taking the center of the wafer as the origin (0,0) with the notchof the substrate directed upward, the region having a width L2 of 2.8 mmand a length L1 of 18.5 mm (a portion other than an edge extrusionportion), to expose the underlying supporting substrate.

[0218] On the exposed region 14, an ID code of 10 digits was recorded bya laser marker SL47 (manufactured by NEC Co.). The laser power was 220mW. The size of the alphanumerical characters was Height: 1.624 ± 0.025mm Breadth: 0.812 ± 0.025 mm Line boldness: 0.200 + 0.050 mm to0.200-0.150 mm Character interval: 1.420 ± 0.025 mm

[0219] in accordance with the SEMI Standard.

[0220] The size of the character can be adjusted by about 0.8 mm-pitch,and may be smaller, or larger for easy reading. When smaller charactersare used, the region of the SOI structure removal is made smaller todecrease the unnecessary removal and to increase the number of theproduced chips.

EXAMPLE 2

[0221] In the peripheral region 13 of a commercially available bondingSOI wafer where the underlying supporting substrate is exposed, an IDcode of 12 digits was recorded by a laser marking apparatus. The12-digit characters were arranged in a line. The laser power was 220 mW.The size of the alphanumerical characters was Height: 1.624 ± 0.025 mmBreadth: 0.812 ± 0.025 mm Line boldness: 0.200 + 0.050 mm to 0.200-0.150mm Character interval: 1.420 ± 0.025 mm

[0222] in accordance with the SEMI Standard.

[0223] The size of the character can be adjusted by about 0.8 mm-pitch,and may be smaller, or larger for easy reading. When the breadth of theperipheral removal region is small, smaller characters are preferred.

EXAMPLE 3

[0224] In a peripheral region of a commercially available SOI waferwhere the supporting substrate was covered only by an oxide film, an IDcode of 12 digits was recorded by a laser marking apparatus. The laserpower was adjusted to 300 mW. The recessed portion caused by the laserpenetrated through the oxide film and reached the supporting substrate.The size of the alphanumerical characters was Height: 1.624 ± 0.025 mmBreadth: 0.812 ± 0.025 mm Line boldness: 0.200 + 0.050 mm to 0.200-0.150mm Character interval: 1.420 ± 0.025 mm

[0225] in accordance with the SEMI Standard.

[0226] The size of the character can be adjusted by about 0.8 mm-pitch,and may be smaller, or larger for easy reading. When the peripheralremoval region is narrow, smaller characters are preferred.

[0227] For special uses, the SEMI Standard need not be applied.

EXAMPLE 4

[0228] A first single-crystalline Si substrate having a specificresistance of 0.01 Ω·cm was anodized in an HF solution. The anodizationconditions were as below. Current density: 7 (mA · cm⁻²) Anodizationsolution: Hydrofluoric acid:water:ethanol = 1:1:1 Time: 11 (minutes)Porous Si thickness: 12 (μm)

[0229] The thickness of the porous layer is not limited thereto and maybe varied in the range from several hundred μm to about 0.1 μm.

[0230] This substrate was oxidized at 400° C. in an oxygen atmosphere tocover the inside walls of the pores of the porous silicon with a thermaloxidation film. The surface of the porous Si layer was treated withhydrofluoric acid to remove the oxide film from only the surface of theporous Si layer while the oxide film on the inside walls of the poreswas kept unremoved. On the porous Si, single-crystalline Si is grownepitaxially by CVD in a thickness of 0.3 μm. The growth conditions wereshown below. Source gas: SiH₂Cl₂/H₂ Gas flow rate: 0.5/180 L/min Gaspressure: 1.1 × 10⁴ Pa (about 80 Torr) Temperature: 950° C. Growth rate:0.3 μm/min

[0231] Prior to the epitaxial growth by introduction of the source gas,the substrate was heat-treated (prebaked) in a hydrogen atmosphere inthe epitaxial growth chamber.

[0232] On the surface of this epitaxial Si layer, an oxide film (SiO₂layer) of 200 nm was formed by thermal oxidation.

[0233] The surface of resulting the SiO₂ layer and the surface of aseparately prepared second Si substrate were brought into contact witheach other, and the contacted substrates were heat-treated at atemperature of 1100° C. for 2 hours to bond the two substrates.

[0234] Most portion of the first substrate side of the bonded substrateswas removed by grinding, and the remaining portion was removed byreactive ion etching to expose the porous Si layer.

[0235] The porous Si layer transferred to the second substrate wasetched by a mixture of 49 wt % hydrofluoric acid, aqueous 30 wt %hydrogen peroxide and water with stirring. The single-crystalline Si wasremained unetched, while the porous Si was completely removed byselective etching.

[0236] Thus a single-crystalline Si layer of 0.2 μm thick was formed onthe Si oxide film. No change was caused in the single-crystalline Silayer by selective etching of the porous Si. The thickness of the formedsingle-crystalline Si layer had uniformity in the range of 201 nm ±4 nmin thickness measurement at 100 points over the entire surface.

[0237] No additional crystal defect was observed in the Si layer bytransmission electron microscopy, and the excellent crystallinity wasconfirmed to be maintained.

[0238] Further, a heat treatment was conducted at 1100° C. in a hydrogenatmosphere for one hour. By observation with an atomic force microscope,the surface roughness was about 0.2 mn in terms of mean square roughnessin a region of 50 μm square, which was equal to the surface roughness ofan ordinary commercial Si wafer.

[0239] Then the Si layer and the SiO₂ layer in the peripheral region of3 mm in width inward from the outer peripheral edge were removed bypatterning to correct the shape of the peripheral portion.

[0240] On the peripheral 3 mm-region, near the notch portion, 12-digitalphanumeric characters were recorded by a laser marking apparatus. Noincrease of deposited particles was observed on SOI wafer.

Example 5

[0241] A first single-crystalline Si substrate of a P-type having aspecific resistance of 0.01 Ω·cm was anodized in an HF solution. Theanodization conditions were as below:

[0242] First stage Current density: 7 (mA · cm⁻²) Anodization solution:Hydrofluoric acid:water:ethanol = 1:1:1 Time: 5 (minutes) First porouslayer thickness: 5.5 (μm)

[0243] Second stage Current density: 30 (mA · cm⁻²) Anodizationsolution: Hydrofluoric acid:water:ethanol = 1:1:1 Time: 10 (seconds)Second porous layer thickness: 0.2 (μm)

[0244] This substrate was oxidized at 400° C. for one hour in an oxygenatmosphere to cover the inside walls of the pores of the porous siliconwith a thermal oxidation film. The surface of the porous Si layer wastreated with hydrofluoric acid to remove the oxide film from only thesurface of the porous layer while the oxide film on the inside walls ofthe pores was kept unremoved. On the porous silicon, single-crystallinesilicon was grown epitaxially by CVD (chemical vapor deposition) in athickness of 0.3 μm. The growth conditions were shown below. Source gas:SiH₂Cl₂/H₂ Gas flow rate: 0.5/180 L/min Gas pressure: 1.1 × 10⁴ Pa(about 80 Torr) Temperature: 950° C. Growth rate: 0.3 μm/min

[0245] Prior to the epitaxial growth, the substrate was heat-treated ina hydrogen atmosphere in the epitaxial growth chamber. By this heattreatment, the crystal defects in the epitaxially grown layer weredecreased to not more than 10⁴ cm⁻².

[0246] On the surface of this epitaxial Si layer, an oxide film (SiO₂layer) of 200 nm thick was formed as an insulating layer by thermaloxidation.

[0247] The surface of the resulting SiO₂ layer and the surface of aseparately prepared second Si substrate were brought into contact andsuperposition with each other, and the superposed substrates wereheat-treated at a temperature of 1100° C. for 2 hours to cause bonding.

[0248] The above bonded substrates were separated at the porous Si layerby solid wedge insertion and water wedge insertion by water-jet.

[0249] The porous Si layer transferred to the second substrate wasetched selectively by a mixture of 49 wt % hydrofluoric acid, aqueous 30wt% hydrogen peroxide and water with stirring.

[0250] Thus a single-crystalline Si layer of 0.2 μm thick was formed onthe Si oxide film. No change was caused in the single-crystalline Silayer by the selective etching of the porous Si. The thickness of theformed single-crystalline Si layer had uniformity in the range of 201nm±4 nm in thickness measurement at 100 points over the entire surface.

[0251] No additional crystal defect was observed in the Si layer bytransmission electron microscopy, and the excellent crystallinity wasconfirmed to be maintained.

[0252] Further, a heat treatment was conducted at 1100° C. in a hydrogenatmosphere for one hour. By observation with an atomic force microscope,the surface roughness was about 0.2 mn in terms of mean square roughnessin a region of 50 μm square, which was equal to the surface roughness ofan ordinary commercial Si wafer.

[0253] Then the Si layer and the SiO₂ layer in the peripheral region of2.5 mm in width inward from the outer peripheral edge were removed bypatterning to correct the shape of the peripheral portion.

[0254] On the peripheral region, near the notch portion, 12-digitalphanumeric characters were recorded by a laser marking apparatus. Noincrease of deposited particles was observed on the SOI wafer. The laserpower was 220 mW. The size of the alphanumerical characters was Height:1.624 ± 0.025 mm Breadth: 0.812 ± 0.025 mm Line boldness: 0.200 + 0.050mm to 0.200-0.150 mm Character interval: 1.420 ± 0.025 mm

[0255] in accordance with the SEMI Standard.

[0256] The porous Si remaining on the first substrate side wasselectively etched by the aforementioned liquid mixture of hydrofluoricacid, hydrogen peroxide and water. The substrate was annealed withhydrogen. Thereby the substrate was made reusable as the first substrateor the second substrate.

Example 6

[0257] A first single-crystalline Si substrate of a P-type having aspecific resistance of 0.01 Ω·cm was anodized in an HF solution. Theanodization conditions were as below:

[0258] First stage Current density: 7 (mA · cm⁻²) Anodization solution:Hydrofluoric acid:water:ethanol = 1:1:1 Time: 5 (minutes) First porouslayer thickness: 5.5 (μm)

[0259] Second stage Current density: 30 (mA · cm⁻²) Anodizationsolution: Hydrofluoric acid:water:ethanol = 1:1:1 Time: 10 (seconds)Second porous layer thickness: 0.2 (μm)

[0260] This substrate was oxidized at 400° C. for one hour in an oxygenatmosphere to cover the inside walls of the pores of the porous siliconwith a thermal oxidation film. The surface of the porous Si layer wastreated with hydrofluoric acid to remove the oxide film from only thesurface of the porous layer while the oxide film on the inside walls ofthe pores was kept unremoved. On the porous silicon, single-crystallinesilicon was grown epitaxially by CVD in a thickness of 0.3 μm. Thegrowth conditions were shown below. Source gas: SiH₂Cl₂/H₂ Gas flowrate: 0.5/180 L/min Gas pressure: 1.1 × 10⁴ Pa (about 80 Torr)Temperature: 950° C. Growth rate: 0.3 μm/min

[0261] Prior to the epitaxial growth, the substrate was heat-treated ina hydrogen atmosphere in the epitaxial growth chamber. By this heattreatment, the crystal defects of the epitaxially grown layer weredecreased to not more than 10⁴ cm⁻².

[0262] On the surface of this epitaxial growth layer, an oxide film(SiO₂ layer) of 200 nm thick was formed as an insulating layer bythermal oxidation.

[0263] Another Si substrate was prepared. On a portion which would bepresent outside the contact edge on the peripheral portion of thissubstrate near the notch, that is, on the surface of peripheral portionof the Si substrate slightly inclined by beveling, alphanumericalcharacters of 12 digits were recorded by a laser marking apparatus. Thelaser power was 220 mW. The size of the alphanumerical characters wasHeight: 1.624 ± 0.025 mm Breadth: 0.812 ± 0.025 mm Line boldness:0.200 + 0.050 mm to 0.200-0.150 mm Character interval: 1.420 ± 0.025 mm

[0264] in accordance with the SEMI Standard.

[0265] The substrate after the laser marking was cleaned.

[0266] The surface of the SiO₂ layer of the first substrate and thesurface of the marked second Si substrate were brought into contact witheach other, and were heat-treated at 1100° C. for 2 hours for bonding.According to analysis, the bonding was found not to be caused at themarked portion.

[0267] The above bonded substrates were separated at the interior of theporous Si layer by solid wedge insertion and water wedge insertion bywater-jet.

[0268] The porous Si layer transferred to the second substrate wasetched selectively by a mixture of 49 wt % hydrofluoric acid, aqueous 30wt % hydrogen peroxide and water with stirring.

[0269] Thus a single-crystalline Si layer of 0.2 μm thick was formed onthe Si oxide film. No change was caused in the single-crystalline Silayer by the selective etching of the porous Si. The thickness of theformed single-crystalline Si layer had uniformity in the range of 201nm±4 nm in thickness measurement at 100 points over the entire surface.

[0270] No additional crystal defect was observed in the Si layer bytransmission electron microscopy, and the excellent crystallinity wasconfirmed to be maintained.

[0271] Further, a heat treatment was conducted at 1100° C. in a hydrogenatmosphere for one hour. By observation with an atomic force microscope,the surface roughness was about 0.2 mn in terms of mean square roughnessin a region of 50 μm square, which was equal to the surface roughness ofan ordinary commercial Si wafer.

[0272] Then the SOI layer in the peripheral region of 2.5 mm in widthinward from the outer peripheral edge, and SiO₂ in the peripheral regionof 2.3 mm in width inward from the outer peripheral edge were removed bypatterning to correct the shape of the peripheral portion.

[0273] Since the marked portion had not been bonded, the marked portionwas hardly deformed in the steps of separation, etching, and so forth.

[0274] As described above in detail, in each of Examples, the particlegeneration is retarded since the mark is formed by laser marking on theregion which does not have an SOI multilayer structure. Further, thelaser power need not be adjusted for optimization for the SOI layercombination, regardless of the SOI layer structure.

[0275] The particle generation is one of the main causes of drop of thedevice production yield. In particular, under the rule of not more than0.1 μm at present, even slightest particle generation or a smallestparticle generation is not acceptable. In such a circumstance, particlegeneration can be prevented to a certain extent by adjusting the laserpower and other conditions in accordance with the SOI layer thicknessconstitution. However, this decreases the production yield in massproduction. Therefore, if the marking can be conducted under fixedconditions regardless of the SOI film thickness constitution, theparticle increase can be made minimum.

[0276] The present invention provides a semiconductor substrate whichfacilitates the reading of the ID mark and causes less deposition ofsplashed particles, and on which the marking of the ID is easilyconducted.

[0277] In the above-mentioned embodiments or examples, it may beemployed any conditions as below:

[0278] 1) bonding anneal;

[0279] atmosphere/O₂, N₂,

[0280] temperature/400° C. to 1100° C.,

[0281] 2 steps annealing,

[0282] 2) prebonding treatment;

[0283] nitrogen plasma treatment and pure water rinsing,

[0284] 3) anodization;

[0285] HF solution with ethanol or isopropanol,

[0286] 4) H₂ annealing;

[0287] temperature/800° C. to 1150° C. or more,

[0288] 5) Marking;

[0289] adjusting/laser power, shot counts, pulse width, beam diameter,dot diameter, dot depth, etc. Depth of the mar/1 μm to 400 μm.

[0290] The present invention may be embodied in other specific formswithout departing from the spirit or essential characteristics thereof.The present examples are therefore to be considered in all respects asillustrative and not restrictive, the scope of the present inventionbeing indicated by the appended claims rather than by the foregoingdescription and all changes which come within the meaning and range ofequivalency of the claims are therefore intended to be embraced therein.

What is claimed is:
 1. A semiconductor substrate comprising asemiconductor layer formed on a supporting substrate with interpositionof an insulating layer therebetween, wherein a mark is formed in aregion other than the surface region of the semiconductor layer.
 2. Thesemiconductor substrate according to claim 1, wherein the mark is atleast one selected from the group consisting of numerals, characters,symbols, and bar codes.
 3. The semiconductor substrate according toclaim 1, wherein the region to be marked is a peripheral region of thesupporting substrate where the semiconductor layer is not present. 4.The semiconductor substrate according to claim 3, wherein an outsideborder line of the peripheral region is an outer peripheral edge of thesupporting substrate, and an inside border line of the peripheral regionis at a position of 1 mm or more inside from the outer peripheral edgeof the supporting substrate.
 5. The semiconductor substrate according toclaim 1, wherein the region to be marked is in an internal region of thesupporting substrate, where the semiconductor layer is not locallypresent.
 6. The semiconductor substrate according to claim 1, whereinthe region to be marked is on the back surface side of the supportingsubstrate.
 7. The semiconductor substrate according to claim 1, whereinthe mark is formed near a notch or an orientation flat.
 8. Thesemiconductor substrate according to claim 1, wherein the mark is formedby making a recessed portion and/or a protruded portion.
 9. Thesemiconductor substrate according to claim 1, wherein the mark is formedby laser.
 10. The semiconductor substrate according to claim 1, whereinthe mark is formed by engraving a surface.
 11. The semiconductorsubstrate according to claim 1, wherein the semiconductor substrate isan SOI substrate.
 12. The semiconductor substrate according to claim 11,wherein the SOI substrate is a bonding SOI substrate.
 13. Thesemiconductor substrate according to claim 12, wherein the bonding SOIsubstrate has the semiconductor layer separated at an ion-implantedlayer formed by implantation of hydrogen and/or an inert gas.
 14. Thesemiconductor substrate according to claim 12, wherein the bonding SOIsubstrate has the semiconductor layer formed by transferring a nonporoussemiconductor layer formed on a porous material onto the supportingsubstrate.
 15. The semiconductor substrate according to claim 11,wherein the SOI substrate has the insulating layer formed byimplantation of oxygen and/or nitrogen ions and teat treatment.
 16. Aprocess for producing a semiconductor substrate comprising asemiconductor layer formed on a supporting substrate with interpositionof an insulating layer therebetween, the process comprising a step offorming a mark in a region other than a surface region of thesemiconductor layer.
 17. The process for producing a semiconductorsubstrate according to claim 16, wherein at least one selected from thegroup consisting of numerals, characters, symbols, and bar codes isengraved as the mark.
 18. The process for producing a semiconductorsubstrate according to claim 16, wherein the region to be marked is aperipheral region of the supporting substrate where the semiconductorlayer is not present.
 19. The process for producing a semiconductorsubstrate according to claim 18, wherein an outside border line of theperipheral region is an outer peripheral edge of the supportingsubstrate, and an inside border line of the peripheral region is at aposition of 1 mm or more inside from the outer peripheral edge of thesupporting substrate.
 20. The process for producing a semiconductorsubstrate according to claim 16, wherein the region to be marked is aninternal region of the supporting substrate where the semiconductorlayer is not locally present.
 21. The process for producing asemiconductor substrate according to claim 16, wherein the region to bemarked is a back surface side of the supporting substrate.
 22. Theprocess for producing a semiconductor substrate according to claim 16,wherein the mark is formed near a notch or an orientation flat.
 23. Theprocess for producing a semiconductor substrate according to claim 16,wherein the mark is formed by making a recessed portion and a protrudedportion.
 24. The process for producing a semiconductor substrateaccording to claim 16, wherein the mark is formed by laser light. 25.The process for producing a semiconductor substrate according to claim16, wherein the mark is formed by engraving a surface.
 26. The processfor producing a semiconductor substrate according to claim 16, whereinthe semiconductor substrate is an SOI substrate.
 27. The process forproducing a semiconductor substrate according to claim 26, wherein theSOI substrate is a bonding SOI substrate.
 28. The process for producinga semiconductor substrate according to claim 27, wherein the bonding SOIsubstrate is formed by implanting hydrogen and/or inert gas ions into afirst substrate, bonding the first substrate to a second substrate asthe supporting substrate, and separating the first substrate from thesecond substrate at a separation layer formed by the implantation of theions.
 29. The process for producing a semiconductor substrate accordingto claim 28, wherein the first substrate has a semiconductor layerformed by epitaxial growth.
 30. The process for producing asemiconductor substrate according to claim 28, further comprising a stepof smoothening a surface of the separated substrate by hydrogenannealing and/or polishing.
 31. The process for producing asemiconductor substrate according to claim 27, wherein the bonding SOIsubstrate has the semiconductor layer formed by transferring a nonporoussemiconductor layer formed on a porous material onto the supportingsubstrate.
 32. The process for producing a semiconductor substrateaccording to claim 31, wherein the formation of the bonding SOIsubstrate is further conducted by removing the porous layer andsubsequently smoothening a surface of the semiconductor layer byhydrogen annealing and/or polishing.
 33. The process for producing asemiconductor substrate according to claim 31, further comprising a stepof removing a peripheral portion of the transferred semiconductor layer.34. The process for producing a semiconductor substrate according toclaim 31, wherein the removal of the porous material includes a step ofseparating the bonding SOI substrate at a layer of the porous material,and a step of etching the porous material remaining on a separationsurface of the nonporous semiconductor layer.
 35. The process forproducing a semiconductor substrate according to claim 27, wherein thebonding SOI substrate having the semiconductor layer is formed bypreparing a first substrate constituted of a nonporous substrate and anonporous semiconductor formed thereon with interposition of a layer ofa porous material therebetween, bonding the first substrate to a secondsubstrate as the supporting substrate, and separating the first and thesecond substrates at the layer of the porous material to transfer thenonporous semiconductor layer to the supporting substrate.
 36. Theprocess for producing a semiconductor substrate according to claim 35,wherein the bonding SOI substrate having the semiconductor layer isformed by forming a layer of a porous material on a nonporous substrateby anodization, forming a protective film on inside walls of pores inthe porous material, conducting hydrogen baking, growing epitaxially anonporous semiconductor layer on the layer of the porous material,forming an insulating layer on the surface thereof to provide a firstsubstrate, bonding the first substrate to a second substrate as thesupporting substrate, separating the first and the second substrate atthe layer of the porous material, removing the porous material remainingthe separation surface of the second substrate, and smoothening anexposed surface of the nonporous semiconductor layer.
 37. The processfor producing a semiconductor substrate according to claim 35, whereinthe bonded substrates are separated by inserting a solid and/or fluidwedge.
 38. The process for producing a semiconductor substrate accordingto claim 35, wherein the bonded substrates are separated by applying atleast one of pressure, pulling force, shearing force, and ultrasonicvibration.
 39. The process for producing a semiconductor substrateaccording to claim 27, wherein the bonding SOI substrate having thesemiconductor layer is formed by preparing a first substrate constitutedof a nonporous substrate and a nonporous semiconductor layer formedthereon with interposition of a layer of a porous material therebetween,bonding the first substrate to a second substrate as the supportingsubstrate, and removing the nonporous substrate and the porous materialby at least one of grinding, polishing and etching to transfer thenonporous semiconductor layer to the supporting substrate.
 40. Theprocess for producing a semiconductor substrate according to claim 26,wherein the SOI substrate has the insulating layer formed byimplantation of oxygen and/or nitrogen ions and heat treatment.
 41. Theprocess for producing a semiconductor substrate according to claim 40,further comprising a step of partially removing the semiconductor layer.42. A process for producing a semiconductor substrate comprising asemiconductor layer formed on a supporting substrate with interpositionof at least one layer therebetween, the process comprising a step offorming a mark in a region other than a surface region of thesemiconductor layer.
 43. A semiconductor substrate having asemiconductor layer formed on a supporting substrate with interpositionof at least one layer therebetween, wherein a mark is formed in a regionother than a surface region of the semiconductor layer.
 44. Thesemiconductor substrate according to claim 1, wherein the semiconductorsubstrate is a bonding SOI substrate, and the mark is formed on asurface of the supporting substrate where bonding is not conducted. 45.The semiconductor substrate according to claim 1, wherein thesemiconductor substrate is a bonding SOI substrate, and the mark isformed on a surface of the supporting substrate outside a positioncorresponding to a contact edge.
 46. The semiconductor substrateaccording to claim 1, wherein the semiconductor substrate is a bondingSOI substrate, and the mark is formed on a surface of the supportingsubstrate outside a position corresponding to a contact edge or abonding edge.
 47. The semiconductor substrate according to claim 1,wherein the semiconductor substrate is a bonding SOI substrate, and themark is formed on a surface of the supporting substrate where a bondingedge is locally moved inward from an outer peripheral portion of thesupporting substrate comparative to the other bonding edge.
 48. Theprocess for producing a semiconductor substrate according to claim 16,wherein the mark is formed in a state of covering the surface region ofthe semiconductor layer with a film other than the semiconductor layer.49. The process for producing a semiconductor substrate according toclaim 16, wherein the mark is formed in a state of covering the surfaceregion of the semiconductor layer with a layer of a porous material. 50.The process for producing a semiconductor substrate according to claim16, wherein the mark is formed in a state of covering the surface regionof the semiconductor layer with a mask for shaping a peripheral region.51. The process for producing a semiconductor substrate according toclaim 16, further comprising a step of preparing a first substrate and asecond substrate having the mark formed thereon, and a step oftransferring a layer to be transferred of the first substrate by bondingthe first substrate and the second substrate and by removing anunnecessary portion of the first substrate.
 52. The process forproducing a semiconductor substrate according to claim 16, furthercomprising a step of preparing a first substrate, forming the mark on aperipheral portion of a second substrate, and a step of transferring alayer to be transferred of the first substrate by bonding the firstsubstrate and the second substrate without bonding at the marked portionand by removing an unnecessary portion of the first substrate.
 53. Theprocess for producing a semiconductor substrate according to claim 16,further comprising a step of preparing a first substrate, forming themark on a peripheral portion of a second substrate, and a step oftransferring a layer to be transferred of the first substrate by bondingthe first substrate and the second substrate so as to bring a contactedge or a bonding edge to a position inside the marked portion and byremoving an unnecessary portion of the first substrate.
 54. The processfor producing a semiconductor substrate according to claim 16, furthercomprising a step of preparing a first substrate, forming the mark on aperipheral portion of a second substrate, and a step of transferring alayer to be transferred of the first substrate by bonding the firstsubstrate and the second substrate so as to locally bring a bonding edgeinside the marked portion and by removing an unnecessary portion of thefirst substrate.
 55. The process for producing a semiconductor substrateaccording to claim 36, wherein the bonded substrates are separated byinserting a solid and/or fluid wedge.
 56. The process for producing asemiconductor substrate according to claim 36, wherein the bondedsubstrates are separated by applying at least one of pressure, pullingforce, shearing force, and ultrasonic vibration.